The present invention relates generally to integrated circuits (ICs). More particularly, the present application relates to a process for preventing deformation of patterned features on a layer of photoresist material utilized for IC fabrication.
The semiconductor or integrated circuit (IC) industry aims to manufacture ICs with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration requires continued shrinking of circuit dimensions and device features. The ability to reduce the size of structures, such as, gate lengths in field-effect transistors and widths of conductive lines, is driven by lithographic performance.
IC fabrication often utilizes a mask or reticle to form an image or pattern on one or more layers comprising a semiconductor wafer. Radiation is provided or reflected off the mask or reticle to form the image on the semiconductor wafer. The wafer is correspondingly positioned to receive the radiation transmitted through or reflected off the mask or reticle. The radiation can be light at a wavelength in the ultraviolet (UV), vacuum ultraviolet (VUV), deep ultraviolet (DUV), or extreme ultraviolet (EUV) range. The radiation can also be a particle beam such as an x-ray beam, an electron beam, etc.
Typically, the image on the mask or reticle is projected and patterned onto a layer of photoresist material disposed over the wafer. The areas of the photoresist material upon which radiation is incident undergo a photochemical change to become suitably soluble or insoluble in a subsequent development process. In turn, the patterned photoresist layer is used to define doping regions, deposition regions, etching regions, and/or other structures comprising the IC.
As patterned photoresist features achieve ever smaller lateral dimensions, its aspect ratio (i.e., height/width) correspondingly increases. Unfortunately, patterned photoresist features with aspect ratios xe2x89xa73.0 have a tendency to mechanically or physically deform during etch processes. As shown in FIGS. 1A-1D, a patterned photoresist feature 100 (e.g., a conductive line) undergoing an etch process (e.g., a resist trimming process or an etch process involving an underlying layer of the wafer) can suffer a number of failure mechanisms, such as, a pattern bending 102, a pattern breakage 104, or a pattern collapse 106. Such mechanical deformations are caused by capillary forces, inadequate inherent mechanical stability of feature 100, and/or the impact of etchant species on feature 100.
This tendency toward mechanical deformation is even more prevalent in photoresist materials that inherently have poor mechanical stability. Unfortunately, photoresist materials designed for shorter wavelength lithography exhibit poor mechanical stability. For example, currently available 193 nanometer (nm) photoresist materials based on acrylate and cyclo-olefin polymers have low mechanical stability compared to 248 nm photoresist materials based on phenolic polymers.
Since poor mechanical stability increases the likelihood of mechanical deformations during a given etch process, mechanical stability also correlates with etch stability. And indeed, 193 nm photoresist materials have a lower etch stability in comparison to their 248 nm counterparts and are more difficult to maintain pattern integrity through an etch process. Accordingly, achieving desirable small lateral dimensions and successful pattern transfer to the underlying layer(s) of the wafer with patterned photoresist features having poor etch stability is difficult.
Thus, there is a need for a process for preventing mechanical deformation of patterned photoresist features during etch processing.
There is a further need for a process for increasing the mechanical stability of patterned photoresist features. There is still a further need for a process for increasing the etch stability of patterned photoresist features.
One exemplary embodiment relates to an integrated circuit fabrication process. The process includes stabilizing a feature patterned on a photoresist layer with an electron beam. The process further includes etching at least one of the photoresist layer and the substrate. The photoresist layer is disposed over a substrate. The stabilizing step is performed before the etching step. The feature patterned on the photoresist layer at the etching step has an aspect ratio greater or equal to 3.0, a vertical thickness greater than 300 nm, or is comprised of an acrylate, alicyclic, or cyclo-olefin based polymer.
Another exemplary embodiment relates a method of maintaining pattern integrity during an integrated circuit fabrication. The integrated circuit fabrication includes a feature patterned on a photoresist layer and at least one potentially pattern deforming processing step. The method includes preventing the feature patterned on the photoresist layer from deforming using a flood electron beam. The method further includes configuring the conditions of the flood electron beam depending on a type of material comprising the photoresist layer, characteristics of the at least one potentially pattern deforming processing step, a vertical thickness of the photoresist layer, or a lateral dimension of the feature patterned on the photoresist layer. The feature patterned on the photoresist layer is selectively exposed to the flood electron beam before at least one potentially pattern deforming processing step.
Still another exemplary embodiment relates to a feature patterned on a photoresist layer. The feature includes a cured region. The cured region prevents the feature from at least one of bending, breaking, collapsing, and deforming during a subsequent etch process.